In general, the present invention relates to a signal-processing circuit employed in a playback system for playing back information from a magnetic recording medium or an optical recording medium. More particularly, the present invention relates to a signal-processing circuit employing a PLL (Phase Locked Loop) circuit inputting playback data obtained as a result of digital conversion of a playback signal through a first equalization circuit, and relates to a recording and playback apparatus employing the signal-processing circuit.
A tape streamer conforming to DDS (Digital Data Storage)-4 specifications typically includes a recording system 110 with a configuration like one shown in FIG. 65 and a playback system 120 with a configuration like one shown in FIG. 66. The recording system 110 records data onto a magnetic tape 130 whereas the playback system 120 plays back data from a magnetic tape 130.
As shown in FIG. 65, in the recording system 110 employed in a tape streamer conforming to the DDS4 specifications, data to be recorded is subjected to 8/10 conversion carried out by an 8/10 converter 111. The 8/10 conversion is a kind of block coding. The data completing the 8/10 conversion is then converted into a current by a recording amplifier 112. The current is supplied to a recording head 114 by way of a rotary transformer 113. Then, the recording head 114 records the data onto the magnetic tape 130.
In the playback system 120 employed in a tape streamer conforming to the DDS4 specifications, on the other hand, a playback RF signal generated by a playback head 121 from the magnetic tape 130 is amplified by a playback amplifier 122 before being supplied to a first equalization circuit 124 by way of a rotary transformer 123 as shown in FIG. 66. In accordance with the DDS4 specifications, partial response class 1 (PR1) is embraced as a channel transfer characteristic. Thus, the transfer characteristic of the first equalization circuit 124 is adjusted so that the transfer characteristic from the recording amplifier 112 employed in the recording system 110 to the output of the first equalization circuit 124 in the playback system 120 becomes similar to a PR1 transfer characteristic shown in FIG. 67. A PLL circuit 125 extracts a channel clock signal from a signal output by the first equalization circuit 124. An ADC (Analog-to-Digital Converter) 126 driven by this channel clock signal samples detection-point voltages of the signal output by the first equalization circuit 124 as shown in FIG. 68.
Sampling data sampled by the ADC 126 is equalized by a second equalization circuit 127 with a higher degree of precision. After an equalization error has been minimized, the sampling data is converted into a binary signal by a viterbi decoder 128. The second equalization circuit 127 plays a role of compensating the first equalization circuit 124 for low precision of the first equalization circuit 124.
That is to say, in the playback system 120 of a tape streamer, the first equalization circuit 124 and the second equalization circuit 127, which are provided at stages respectively preceding and following the PLL circuit 125, carry out 2-stage equalization.
The binary signal produced by the viterbi decoder 128 is subjected to 10/8 conversion in a 10/8 converter 129 into output playback data.
The 10/8 conversion carried out by the 10/8 converter 129 employed in the playback system 120 is processing inverse to the 8/10 conversion carried out by the 8/10 converter 111 employed in the recording system 110.
In the playback system 120 employed in the tape streamer conforming to the DDS4 specifications, by the way, the first equalization circuit 124 employs an analog CR filter and the second equalization circuit 127 employs a digital transversal filter, which is controlled by an adaptive equalization circuit 127A. Provided at a stage preceding the ADC 126, the first equalization circuit 124 processes an analog signal. Thus, the analog CR filter is appropriate for the first equalization circuit 124. Since the second equalization circuit 127 processes digital data, on the other hand, the digital transversal filter is desirable for the second equalization circuit 127.
The analog CR filter and the digital transversal filter have merits and demerits shown in Table 1.
TABLE 1Precision/freedomConfigurationPlaceAnalog CRPoorSimpleStagefilter precedingADCDigitalGoodComplexStagetransversalfollowingfilterADC
As described above, the 2-stage equalization is carried out by the first equalization circuit 124 and the second equalization circuit 127, which are provided at respectively 2 stages preceding and following the PLL circuit 125. In order to make the 2-stage equalization effective, the following precondition must be satisfied.
The SN ratio of a signal output by the first equalization circuit>the operation limit SN ratio of the PLL circuit 125.
That is to say, if the PLL circuit 125 does not operate normally, the second equalization circuit 127 does not operate normally either. Thus, the minimization of an equalization error by the second equalization circuit 127 can no longer be expected.
Typical cases in which the precondition described above is not satisfied are, for example:    Case 1) The equalization precision of the first equalization circuit 124 is low so that an eye pattern goes out of order.    Case 2) The magnitude of the playback signal is small so that the eye pattern goes out of order.
Case 1 is a case in which the playback frequency characteristic set at the factory has inevitably changed due to wear of the playback head 121 or dirt stuck on the playback head 121. Case 2 is a case in which the magnitude of the playback signal has decreased inevitably in the event of an off-track.
In either case, distinction is impossible by eye-pattern observation as shown in FIGS. 69 and 70.
In order to solve the problem of Case 1, there is devised an approach wherein the equalization error of the first equalization circuit 124 is minimized to assure the normal operation of the PLL circuit 125 so that, as a result, the normal operation of the second equalization circuit 127 is also assured to improve reliability.
In order to solve the problem of Case 2, basically, the off-track must be avoided even though minimization of the equalization error is also effective. This is because the eye-pattern confusion of the signal output by the first equalization circuit 124 is confusion caused by a noise and confusion caused by the equalization error. Thus, by providing an approach of minimizing the equalization error of the first equalization circuit 124, the amount of SN-ratio deterioration can be reduced even by a small playback signal so as to assure the normal operation of the PLL circuit 125. As a result, the normal operation of the second equalization circuit 127 is also assured so that the reliability is improved.
In the minimization of an equalization error of the first equalization circuit 124, however, the use of an analog CR filter causes low precision so that there is a limit.
In addition, if a digital transversal filter is used, there exists an algorithm called an LMS (Least Mean Squared) technique, which exhibits a good convergence characteristic. However, there is no excellent algorithm for automatically controlling the analog CR filter.
Furthermore, assume that a digital transversal filter 124C is employed in the first equalization circuit 124 as shown in FIG. 71. Since an analog signal input to the PLL circuit 125 is a precondition, it is necessary to carry out DAC (Digital-to-Analog Conversion) to generate an analog signal. In this case, the first equalization circuit 124 needs to employ also an LPF 124A, an ADC 124B, a DAC 124D and an LPF 124E in addition to the digital transversal filter 124C, raising the cost.
Moreover, a PLL circuit 125 inputting digital data can be employed as shown in FIG. 72. In this case, the ADC 124B and the digital transversal filter 124C must be operated at a sampling frequency equal to a multiple of the channel clock frequency. Typically, the sampling frequency is at least 10 times the channel clock frequency. This is because, as indicated by eye patterns computed for different sampling rates as shown in FIGS. 73 to 77, with a sampling rate equal to merely few times the channel clock frequency, a sampling data train will include no detection-point voltages.
FIG. 73 is a diagram showing a PR1-channel output typical eye pattern computed at an over-sampling rate 2 times the channel clock frequency.
FIG. 74 is a diagram showing a PR1-channel output typical eye pattern computed at an over-sampling rate 3 times the channel clock frequency.
FIG. 75 is a diagram showing a PR1-channel output typical eye pattern computed at an over-sampling rate 4 times the channel clock frequency.
FIG. 76 is a diagram showing a PR1-channel output typical eye pattern computed at an over-sampling rate 6 times the channel clock frequency.
FIG. 77 is a diagram showing a PR1-channel output typical eye pattern computed at an over-sampling rate 10 times the channel clock frequency.
Since they are each a result of simulation, a detection-point voltage is always included in 1 channel period. In the case of an actual playback waveform, however, a detection-point voltage is not always included in 1 channel period. For an over-sampling rate 10 times the channel clock frequency, a voltage in the vicinity of a detection point is included. In the case of an over-sampling rate 6 or fewer times the channel clock frequency, however, sampling points are too sparse, resulting in a big error.
It is thus necessary to increase the over-sampling rate. However, a high over-sampling rate raises a problem of a difficulty to implement a high-magnification-frequency clock circuit and a problem of rising power consumption.
In addition, with the contemporary technology wherein an analog filter is required at a stage preceding the PLL circuit 125, only the following 2 choices are available:    1. adoption of a 2-chip configuration comprising an analog IC and a digital IC    2. utilization of a BICMOS (BIpolar Complementary Metal Oxide Semiconductor) process to manufacture an analog-digital hybrid IC
The 2-chip configuration entails a high cost and is thus not suitable for a small-size product. In addition, the amount of power consumed by the analog IC is large. On the other hand, the BICMOS process is also costly. In addition, there is also raised a problem that the design periods of both the analog and BICMOS processes are also longer than a CMOS digital IC.